It's financial analyst day at chip designer and seller (but no longer wafer baker) Advanced Micro Devices, and that's reason enough for the company to divulge a few more details about its future Opteron processors and related chipsets and platforms, due early next year.
First of all, the official names of the processors. The "Magny-Cours" chips, which AMD has been chatting up as a game changer for its server business in 2010, will be known as the Opteron 6100 line, while the "Lisbon" processors, which will follow them to market a little bit later, will be called the Opteron 4100s.
The Opteron 6100s will be available in two-socket and four-socket configurations (known as the "Maranello" platform) using AMD's own "Fiorano" chipsets, which El Reg told you all about in September. The Opteron 6100s will are essentially tweaked versions of the current six-core "Istanbul" Opteron 8400 series chips that are equipped with DDR3 memory controllers on the die, plunked side-by-side in a single chip package, and plugged into a new G34 socket.
AMD plans to have versions of the Opteron 6100s with eight cores activated (with four of them being duds, presumably two per physical chip) as well as the full twelve-core complement, something it has been saying for nearly a year now.
Aside from the official name of the Magny-Cours chip, the big news - and the one that will allow AMD to get some traction in the server racket - is the big leap in memory bandwidth that AMD will show in the jump from Istanbul to Magny-Cours systems. According to John Fruehe, director of server product marketing at AMD, there is enough cores and memory bandwidth in the Opteron 6100 series that the company doesn't believe it has to create an eight-socket server. Indeed, the Fiorino chipsets only support eight-way configurations with the current Istanbul processors, but max out at four sockets with the Magny-Cours.
Here's why Fruehe is not worried about scalability. Using the Stream memory bandwidth benchmark as a guide, a four-socket Opteron 6100 box using the SR5690 I/O hub and SP5100 south bridge (which together have support for hot plug PCI-Express 2.0 peripherals and which offer 42 PCI lanes) is able to hit 100 GB/sec of performance.
That is not just a lot of memory bandwidth for a four-socket box, but compares favorably to the eight-socket servers on the market today using Istanbuls, which delivered a little north of 80 GB/sec on the Stream test; a four-socket Istanbul machine delivers just over 40 GB/sec today, and a two-socket server using Intel's "Nehalem EP" Xeon 5500s comes in at around 35 GB/sec.
QuickPath v HyperTransport
You can see why Intel has been taking back market share in the server space with that kind of bandwidth, which is more than three times what its prior Xeon 5400 quad-core chips could deliver because of the technically inferior frontside bus. The QuickPath Interconnect, an homage to AMD's HyperTransport, has allowed Intel to take back some market share.
But it looks like AMD is going to get a turn to eat a few points of share with the Opteron 6100s on two socket systems thanks to a 50 GB/sec rating on the Stream test. The current Istanbul 2400 series chips deliver just north of 20 GB/sec of memory bandwidth on the stream test, which is pathetic compared to the Nehalem machines.
That 100 GB/sec of memory bandwidth in the forthcoming four-socket Opteron 6100 machine is one of the reasons why AMD decided not to do eight-socket configurations with these chips. "It is a lot of development work for a not very large market," says Fruehe, who reckons that there are only about 1,800 x64-based eight-socket servers sold worldwide each quarter and that the number is dwindling as four-socket boxes get more powerful.
"Intel is raving about having 15 different designs for its upcoming Nehalem EX machines, but how many is each vendor going to get out of those 1,800 units?" Fruehe says that the 8P boxes account for less than two-tenths of a percent of current shipments each quarter, and that while 4P boxes are only accounting for around 4 per cent, "even though it is a small space, AMD needs to be there."
The Opteron 6100s are set to ship at the end of the first quarter of next year, and were originally due in the second quarter. But the revamping of AMD's chip design, manufacturing, and testing processes after it screwed up the "Barcelona" quad-core Opteron launch in the fall of 2007 has allowed it to deliver three generations of Opterons since then earlier than planned. (Of course, a cynic might say that AMD is really just managing expectations and giving itself some buffers). "We have Magny-Cours samples out to our partners, and it is looking very healthy," says Fruehe.
The Opteron 6100 series chips are implemented using the same 45 nanometer processes that GlobalFoundries, AMD's wafer baker, used to make the Istanbul Opterons. The Opteron 6100s will come in standard thermal envelope parts (75 watts) as well as in Special Edition versions (slightly higher clock speeds at 95 watts) and Highly Efficient versions (slightly lower clocks and lower voltages at 55 watts). Clock speeds have not been divulged for the chips.
And now to San Marino...
AMD has said precious little about the "San Marino" server platform and its Lisbon processors, now known as the Opteron 4100. Up until today, we did know that the Lisbon chips would have four or six cores and would be available in single-socket and dual-socket machines with two memory channels per socket instead of the four in the Opteron 6100s.
In late September, AMD expanded its homegrown Fiorano server chipset to include geared-down I/O hubs - the SR5650 and the SR5670 - that are paired with the SP5100 southbridge. These two new chipsets, as El Reg explained in September, have fewer PCI Express lanes and engines for peripheral processing, but they burn a bit less juice too, which is important for hyperscale computing environments where there are tens or hundreds of thousands of servers deployed. Every little bit of juice used and heat dissipated adds up.
As it turns out, to get the price of the San Marino platform low, the C32 processor socket that the Opteron 4100 series of chips will use will be a tweaked version of the 1,207-pin Rev F socket. AMD has a habit of recycling slightly modified sockets - the AM2 socket is a rejiggered Rev E with an extra pin, for instance - and does this because motherboard makers and system designers have lots of experience with established sockets. The C32 socket and its Opteron 4100 chips will be keyed slightly differently so people can't accidentally cram the wrong kind of chip into the socket.
As with the Opteron 6100s, the 4100s will use the same 45 nanometer processes at GlobalFoundries and will come in three power bands: 75 standard parts, 55 watt HE parts, and 35 watt Extremely Efficient (EE) parts. That EE chip, by the way, is 5 watts cooler than its Istanbul cousin, which burns 40 watts.
The other bit of news coming out today from AMD is that the engineers have cooked up a special version of the San Marino platform called "Adelaide," which is a super low-voltage, low cost platform aimed at cloud and hyperscale data centers. The Adelaide platform only supports HT1 links, which burn a lot less power than HT3, and will only support the Opteron 4100 EE part as well.
Only the lowest-power chipset (the SR5650 I/O hub/SP5100 southbridge pairing) is supported, and customers have to use low-voltage DDR3 main memory in the boxes as well. By making all of these changes, Fruehe says that AMD can get the power consumed by a two-socket server platform down by between 10 to 15 watts. That may not seem like a lot, until you are talking about 100,000 servers.
One last thing. The future "Valencia" chip due in 2011, using the new Bulldozer core from AMD, will plug into this 1,207-pin C32 socket. So customers who buy San Marino and Adelaide platforms next year will have a chip with six or eight cores that they can plug into the same boxes without making any other changes. You can find out more about the Bulldozer cores and their future chips here.
The Opteron 4100s are due in the second quarter of 2010. AMD has not been more precise about when in the quarter that might be. ®