Two weeks ago, when Intel once again delayed its quad-core "Tukwila" Itanium processors until early 2010, the company did not give much insight into what the delay was about. It also said nothing about how the continuing delays with Tukwila would affect future Itanium processor rollouts.
Like many of you, I have been trying to comprehend what the nature of the latest delay really is.
I understand why Intel put off the Tukwila launch back in February. This was done as the Tukwila chip was to get a processor socket that was different from the current dual-core "Montecito" and "Montvale" Itanium 9100s, and also different from the future "Poulson" and "Kittson" Itaniums. Itanium server suppliers balked at the idea of supporting a new socket for one generation, so Intel went back to the drawing board to tweak the Tukwila chip so it would fit into the socket to be used by Poulson and Kittson.
Why this wasn't done in late 2007 when the Montvale Itaniums were launched, and people were already guessing that Intel would not make its anticipated delivery of Tukwila in the second half of 2008, is anyone's guess.
It is worth remembering that, in 2005, when all Intel had were single-core "Madison" Itaniums, Intel was saying that Montecito would be out in 2005, Montvale would follow fast on its heels in 2006, and Tukwila would debut in 2007. It also suggested that it would have a range of low-voltage parts too, as standard parts for two-socket and four-socket servers.
It is also worth remembering that making a processor, especially one as complex as Tukwila, is a messy and increasingly expensive bit of work. The stakes are high and mistakes are quite likely deadlier than delays.
With the eight-core "Nehalem EP" Xeon 7500s now being delivered late in 2009 and shipping in systems in early 2010, and both Tukwila and Nehalem EP processors using Intel's "Boxboro" chipset and its related QuickPath Interconnect, it was reasonable to think that the chipset rather than the chips that was somehow the cause of the problem.
Not so, says Alan Priestley, enterprise marketing manager for Intel Europe. The Boxboro chip is not the issue. "It was a change to the processor relating to scaling on certain workloads," Priestley explained, echoing the terse comments that Intel made when it pushed Tukwila out on May 21, and adding that it was related to "heavily threaded and data intensive workloads."
I have no idea what the feature change is that Intel is working on, but I would not be surprised to see something I will call QP Assist. This week, Advanced Micro Devices launched its six-core "Istanbul" Opteron 2400 and 8400 processors. They include a feature called HT Assist, which is short for HyperTransport Assist.
What this feature does is relatively simple. In SMP machines, processors in the chip complex are able to get data from the L3 caches in their neighbours, which is obviously a lot quicker than going out to main memory or disk drives for the data. In the past, a chip looking for data from its neighbours had to broadcast a request to them all, asking if any of them have the data. With HT Assist, AMD has carved out 1 MB of the 6 MB L3 cache on each chip to use it as an L3 cache line directory for the other caches in the complex.
So now, when an application needs data, it can go to its own cache and look up where it is, meaning it doesn't have to broadcast requests for L3 data to the other chips. This cuts down on overhead pretty significantly for memory intensive workloads, and the beauty of the way AMD has implemented it is that it is done in the system BIOS, not in the chip.
No one has said that this is what Intel is doing, mind you. Don't get the wrong idea. But the company has copied damned near every other good idea AMD has had in its Opteron chips, so why not this one, too?
In the past, delays of one generation of Itanium processors have had dramatic effects on the schedules for future Itaniums, but Priestley says that this year's two Tukwila delays have not had any impact on the delivery of Poulson and Kittson Itaniums. I find this hard to believe, but if it is true, it means Tukwila will have a relatively short life, at least compared to Madison, Montecito, and Montvale Itaniums.
Of course, Intel has not been specific about when Poulson and Kittson would be delivered. At the Intel Developer Forum last August, Pat Gelsinger, general manager of Intel's Digital Enterprise Group, said merely that Poulson chips would be based on a new microarchitecture and would use a 32 nanometer process. (Tukwila is implemented in a 65 nanometer process, and Intel is skipping the current 45 nanometer processes used to make Nehalem Xeons and Core i7s for the Itanium line.)
Last August, there was some idle chatter at IDF saying that - given the then pretty substantial delays with Tukwila - Poulson might come to market in late 2009, possibly with four cores, or possibly with six or even eight cores. At the time, Tukwila was expected for shipment by late 2008 and to be shipping in machines in early 2009. Expecting Poulson in 2009 was silly, particularly since the 32 nanometer chip making processes wouldn't be ramped until 2010 and Intel leads processes with Core and Xeon processes. It was reasonable to expect Poulson in late 2010, perhaps, but not late 2009. And Kittson, given the two-year cadence of Itanium chips (when the roadmap is not derailed), would reasonably have been expected in late 2012 or so.
Intel, of course, is not silly enough to give dates for future Itaniums anymore, so it is hard to say if Poulson and Kittson are on track or not. Only the OEMs know for sure.
We'll see what happens. ®