"... can cause system hangs in specific circumstances."

At least AMD aren't shipping buggy chips in the masses, eh.

Like the Intel TLB bugs in core2 is the correct heading.

Intel has very similar bugs in Core2. Google for "Theo De Raadt Core2" for more info. The difference - it continued to ship buggy chips.

No idea which ones are worse.

Depending on the application, it may be more preferable to have the system lock up than to have it "happily" calculate a wrong result. Admitted, in other applications, a system lockup is as catastrophic as a wrong number in others.

I am pentium of borg; division is futile; you will be approximated

I wish the marketing droids of these huge corporations would speak English rather than using their apparently abysmal grasp of the language to lie to the market.

This isn't a stop because it never started and a design error is now an erratum, or have they really stopped distribution after discovering a typo in the manual? How very un-IT of them.

According to an article on Tom's Hardware, which was written at the time of the launch, AMD told everyone about the bug at the launch event.

This article seems to imply the bug was discovered later, which doesn't seem to be true.

So, has El Reg been given a bum steer or is Tom secretly in the pay of AMD?

A 20% decrease in performance just to fix a TLB bug in the 3rd Level Cache. I would doubt removing the 3rd level cache would even cause a 20% performance hit. With cache there is a law of diminishing returns (ok it's quite a bit more complicated than that but lets not make this too technical). THe first level offers a huge speed up, the second level a fair amount of speed up, the third a little speed up and subsequent caches (very rare on any chip) offer very little performance gain.

What on earth are they having to do to get this working?

It's a shame to see AMD like this. They were the great hope against Intel until they decided to spend their cash (okay the banks cash) on ATI. Late Athlons and early Opterons outclassed Intel with a far lower price point. Now their chips look a genereation behind Intel and therfore just cannot compete.

The FDIV bug, which affected a large number of installed processors, silently caused a sightly wrong answer, very occasionally, which could in some circumstance be devastating. The workaround was to replace the chip. Here, apparently, the system just halts and a workaround is available.

Why not just stop with all the freaking bells & whistles that make up the so called "new technology" in semiconductor CPUs. Why not just stick with the good old 700 mhz to 1.5 ghz chips? All this NEW tech stuff just seems to kick AMD in the ass anyways. AMD's manufacturing hinderance just keeps their own foot in their mouths anyways. I'm not against "new technology", just against the new release chips that don't seem to make it until the 3rd or 4th generation of repairs, upgrades & revisions to those CPUs that seem to fail.

Barcelona was originally slated for Feb 2007. Then it slipped to 'summer 2007. Then it slipped to October 2007.

Now we're looking at Jan - or Feb 2008 ?

Late and buggy. Meanwhile, Intel's been shipping quad core for over a year now. Looking at the declining server market share of AMD and increasing market share of Intel, customers no longer care about AMD.

Sun are now (at last) listing Barcelona for the Sunfire X2200 and in the UK at a lower price than a dual core Opteron 2220:

X5284A-Z

AMD Opteron Model 2220, 2.8 GHz: £ 510.00

X5326A-QC-UP1

1 Quad-Core AMD Opteron Model 2347 Processor, 1.9 GHz: £ 450.00

X5326A-QC-UP2

2 Quad-Core AMD Opteron Model 2347 Processor, 1.9 GHz: £ 840.00

Sun Micro hasn't been First Tier in a while. Hint: when you have to do a reverse split to get your stock above $10/share, it's a good sign ya ain't a playa.

On the other hand, Sun + AMD are a match made in heaven. They both have an uncanny knack for losing money.

Thanks for clearing that up (regarding Old News).

AMD:

"we're only shipping Barcelona for specific customer commitments, like larger volume deployments."

Translation:

"We busted a gut to try and get 16,000 chips together so that the Ranger supercomputer at the Texas Advanced Computer Centre could deploy in time for the November Top500. Now we've missed that deadline everyone can wait until we get it sorted out properly."

Chris wrote:

"A 20% decrease in performance just to fix a TLB bug in the 3rd Level Cache. I would doubt removing the 3rd level cache would even cause a 20% performance hit."

I'm guessing that the BIOS workaround had to disable some other stuff as well to stop the system crashing which had a big performance impact.

When the chips are fixed and everything can be turned back on then the performance impact will probably be much smaller.