Intel announced its 'Moorestown' system-on-a-chip platform for UMPCs and internet tablets back in April this year, but it kept the details close to its chest. Now they've leaked out.

Moorestown will comprise two chips: the SoC, codenamed 'Lincroft', and an I/O part called 'Langwell'. According to a report on Japanese-language site PCWatch, Lincroft has an integrated memory controller that connects to a bank of DDR 3 memory.

How Lincroft connects to Langwell remains unclear, but we can say they won't link up over a frontside bus as the current A100/A110 and the upcoming next-gen, 45nm UMPC CPU, 'Sliverthorne', do. Now that we know Intel it looking at a DMI bus to connect its 45nm 'Nahelem'-architecture mobile processors to their I/O chips, it's highly likely the chip giant is planning to use the same technology in Moorestown.

Langwell will incorporate controllers for USB, PCI Express, ATA peripherals and other system basics.

Intel has pledged that Moorestown as a whole will deliver performance enough to run Windows Vista yet consume a twentieth of the power a Celeron M CPU does today, or a fifth of what next year's Silverthorne-based 'Menlow' platform will require.

At the most recent Intel Developer Forum, held last September, the company reiterated its plan to release Moorestown in the 2009/2010 timeframe. The latest roadmap data suggests it may have brought the part's release forward to mid-2009, ahead of the introduction of processors based on the 'Westmere' architecture, the 32nm die-shrink of Nahelem.

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