Intel, lBM, AMD and Sun Microsystems will go coring mad next week as the vendors reveal some of their most impressive future chip designs at the ISSCC (International Solid State Circuits) Conference in San Francisco.
The ISSCC is not for the faint of brain. It brings together the top minds in the chip game whether they concentrate on entire processor designs or improved wires for connecting components. Some of the brightest folks from the Tier 1 vendors have prepped sessions on their latest and greatest multi-core chips, according to the conference's program.
Intel, for example, will shed more detail on its futuristic 80-core chip capable of cranking through 1.28TFlops. The 275mm squared processor has "80 tiles arranged as a 10x8 2D array of floating-point cores and packet-switched routers, operating at 4GHz," Intel writes in its summary of the presentation. "The 65nm 100m transistor die is designed to achieve a peak performance of 1.0TFlops at 1V while dissipating 98W." Ars Technia last year did a nice summary on the chip.
IBM plans to unleash some more of the nit and grit on Power6. "The 700m transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect," IBM writes. "It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications."
The Power6 chip seems to diverge from the high-end server chip designs that Intel and Sun have planned. Intel appears set to release a four-core version of Itanium with the cores running well under 5GHz, while Sun has the 16-core Rock chips coming with even slower cores. Server customers will have quite the range of chips options in 2008.
AMD and Sun will also use ISSCC to add detail on previously announced chips with AMD going over its four-core Opteron and Sun hammering away on the Niagara II chip.
We'll have more on the broad coring next week. ®