Plagued by delays, IBM and Sun Microsystems continue to try and beef up interest in their upcoming server processor lines.

IBM, for example, spent this week hyping its Power6 processor that will slot into the company's Unix and Linux servers. Big Blue once hoped to push the chip out by the end of this year or early 2007, but it will now arrive in mid-2007 and gradually make its way through IBM's server line. The dual-core chip will likely come in at about 5GHz and boast up to 4MB of Level 2 cache per core.

IBM has also confirmed that the two cores will be able to share a monster 32MB L3 cache, while each core will crank through two software threads.

Much of this information had been leaked to the press over the last few months, but IBM confirmed the details at this week's Processor Forum event in San Jose.

In an interview with CNET at the event, IBM noted that Power6 will also have hardware-based support for decimal math functions. That should help improve overall performance by a factor of two to seven over today's software that handles decimal – rather than binary – calculations.

Customers will see the AltiVec instruction set present in the PowerPC line make its way to Power6 as well.

Sun and fellow SPARCer Fujitsu tried to tempt the Processor Forum crowd with a couple of tidbits too.

Fujitsu reckons that its upcoming SPARC64 VI chip will bring twice the integer processing performance per socket of today's SPARC V. On the floating point front, that performance gain jumps to 2.5x.

The SPARC64 VI should ship at 2.4GHz with 6MB of shared cache between its two cores.

Sun and Fujitsu look to ship servers based on the chip in early 2007. They've teamed to share some of the costs around chip design and production as part of an agreement to sell a single SPARC-based server line.

The companies had once promised to get kit out the door by mid-2006.

Sun is looking to get its high-end Rock chip out the door in 2008 and will likely replace the SPARC64 boxes at that time. ®

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