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By | Tony Smith 27th September 2006 18:21

Intel readies SSE 4 for 2007

x86 ISA to be extended with application-specific opcodes too

IDF Intel has said it will extend the x86 instruction set with even more Streaming SIMD Extensions (SSE), this time pledging to add a further 50 instructions to the ISA - the largest number of extra program codes the chip giant's added to the x86 lists since the introduction of SSE 2 with the debut of the Pentium 4 in December 2000.

SSE 4 will debut with 'Penryn', the version of the Core 2 architecture adapted for a 45nm manufacturing process and due to debut in H2 2007. It will be accompanied by other new opcodes called "application-targeted accelerators" (ATA) by Intel

SSE 4's prime focus will be media data processing, as per past SSE instructions. However, Intel said the new version also takes in codes for accelerating the way text and string data are processed.

SSE was launched in February 1999. Back then, Intel built on its MMX integer-oriented instruction set with 70 single instruction, multiple data (SIMD) opcodes intended to boost the Pentium CPU's ability to handle media data. In December 2000, it rolled out SSE 2, adding 144 more instructions, then a further 13 in February 2004 with the debut of SSE 3.

The arrival of the Core 2 Duo processor line this summer saw the addition of 32 more SIMD instructions, but Intel sees these as an extension to SSE 3 rather than a new version of the technology. It dubs them "Supplemental SSE 3" instructions. The Core 2 Extreme has them too.

Intel has so far disclosed only two ATA opcodes, one designed to accelerate data integrity checking algorithms. The other speeds pattern recognition and search routines, the chip maker promised. Again, ATA technology is expected to debut in the Penryn architecture late next year. ®

Read Reg Hardware's complete IDF Fall 06 coverage here

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