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By | Tony Smith 20th September 2005 09:40

Intel tweaks 65nm process to blitz leakage

But there's a catch...

Intel is working on a version of its 65nm chip fabrication process that will produce processors with even lower power consumption characteristics. The chip giant says he technology will reduce transistor leakage by a factor of 1000.

There's a catch: the process halves the processor's potential performance, admitted Intel's director of process architecture and integration, Mark Bohr, in an interview with EETimes.

For that reason, the process, called P1265, will target chips for mobile phones and other mobile devices, so it's a clear candidate for future XScale processors. Intel is scheduled to ship its first 90nm XScale, codenamed 'Monahans', in Q4.

P1265 tweaks Intel's 'standard' 65nm process, P1264, retaining its eight-layer metal structure with copper interconnects. It too uses strained silicon techniques and low-k dielectric insulators. However, the new process raises the transistor's sub-threshold voltage using a "low-dosage implant step", equipping the ultra-shallow junction with a "high-dose implant step followed by an anneal", and thickening the gate oxide layer.

It's the latter component that impacts performance, but Intel clearly believes it has a better chip, in toto . As evidence it quotes leakage current figures: 100nA per micron for the standard 65nm process compared to 0.01nA per micron for P1265. That, the company says, yields "significant" power savings. As for the performance drop, that's relative to 65nm notebook, server and desktop chips, so should be still well in excess of what the company's XScale CPUs are offering today.

P1264 is due to yield shipping Pentium M processors by the end of the year. P1265, on the other hand, won't ramp up to full-scale production until 2007. ®

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