IBM and AMD have found a way to improve transistor performance by up to 24 per cent - without increasing the power draw - using a tweaked implementation of Big Blue's 'strained silicon' process.
The process is not only going to be applied to upcoming AMD64 and PowerPC chips, but is likely to underpin the production of Sony's 'Cell' CPU and future Macintosh computers.
The new technique is called 'dual stress liner' (DSL) and works by not only stretching the silicon lattice in n-type transistors, the usual target of the strained silicon process, but by compressing the lattice in p-type transistors. The latter transport positive charges called 'holes'; n-type transistors operate by moving negatively charged electrons. Straining the lattice makes it easier for electrons to flow. Essentially it's like running through an evenly planted forest - the further apart the trees (the lattice) are, the less likely you (the electron) are to run into one.
Bizarrely, pushing the lattice closer together, while hindering electrons, nevertheless makes its easier for holes to move. Holes are the spaces electrons may occupy, but they can essentially be considered as positively charged particles. In an electric field, they drift along like electrons do, but in the opposite direction. Restricting electron flow, increases the number of places in which they could be located, which is to all intents and purposes the same thing as increasing positive particle flow.
HOT gets hotter
Building on IBM's Strained Silicon Directly on Insulator (SSDOI) technology, DSL likewise uses Germanium to stretch the silicon lattice then removes it before actual chip production takes place, ensuring that its fabrication process doesn't need to be modified to take into account the properties of the straining material. That contrasts with Intel's strained silicon system, in which the Germanium atoms are retained in the chip. It also makes Intel's approach more expensive to do than IBM's.
When IBM announced SSDOI, it also announced a process called Hybrid Orientation Technique (HOT), which improves the mobility of positive charges, or 'holes', in the other direction by combining two substrates on the same wafer, each with different surface orientations.
Together SSDOI and HOT sound an awful lot like DSL. When IBM announced its SSDOI and HOT, in September 2003, it claimed a 40-65 per cent improvement to transistors performance over chips fabbed using a vanilla CMOS process. At this stage, it's not clear whether the 24 per cent gain IBM and AMD are claiming today is in addition to whatever boost SSDOI and HOT ultimately yielded or includes that benefit.
AMD's current 90nm processor line-up already incorporate strained silicon technology, believed to have been supplied by IBM through the two chip makers' January 2003 R&D alliance, although that's primarily centred on developing a joint 65nm process. AMD originally used an alternative approach, from AmberWave, but ultimately rejected it in favour of Big Blue's technology.
DSL is clearly a development of the basic work put in by IBM. Interestingly, it's not only AMD that has had some input into the new process, but Sony and Toshiba too. So DSL will almost certainly have a role to play in the production of 'Cell', the multi-processing oriented CPU being developed by Sony, IBM and Toshiba.
For its part, AMD said it intends to roll out 90nm processors using the new technique during H1 2005, bringing the technique to the production of all its 90nm parts over time. Its future dual-core chips will utilise DSL, it said.
IBM will ship a variety of 90nm Power and PowerPC chips using the technique in the H1 2005 timeframe, too. That may prove good news for Mac users keen to see not only faster G5-class desktops but PowerBook notebooks based on the 64-bit chip.
DSL will be discussed in detail at the 2004 IEEE International Electron Devices Meeting in San Francisco this week. ®
90nm Opterons, Athlons to use strained silicon
AMD to offer strained silicon chips
IBM boffins boost chip performance by 65%
AMD 'super' SOI to boost chip speeds by 30%
AMD dismisses Intel high-k transistor tech
Intel talks up 65nm process with SRAM cell demo
Intel to cut Prescott leakage by 75% at 65nm
AMD and Intel scientists outline future chip tech